Semiconductor manufacturing processes may be divided into a front end of the line (FEOL) process, which may include forming transistors on a silicon substrate, and a back end of the line (BEOL) process, which may include forming an interconnection. In a BEOL process, transistors may be connected to each other to create power supply and signal transmission paths that may form an integrated circuit on a silicon substrate.
For the BEOL process, copper (Cu), which may have high electro-migration (EM), may be used. However, since copper may not be easily etched and may be oxidized during a process, copper may not be easily patterned by a common photolithograph technology. As an alternative, to form a copper metal interconnection, a damascene process may be used. In a dual damascene process a via and a trench in an interlayer dielectric layer may first be formed on a substrate. Then, copper may be buried and may be planarized through a CMP processed.
FIGS. 1A to 1D illustrate a related art dual damascene process.
Referring to FIG. 1A, barrier insulating layer 14 may be formed in first interlayer dielectric layer 10 where a lower metal interconnection 12 may be formed. Barrier insulating layer 14 may function as an etch stop layer in the process of forming a damascene pattern on barrier insulating layer 14, and may include SiN and/or SiC. Second interlayer dielectric layer 16 may be formed on barrier insulating layer 14. After forming second interlayer dielectric layer 16, a damascene pattern, which may include via 16a and trench 16b, may be formed on second interlayer dielectric layer 16, and may use barrier insulating layer 14 as the etch stop layer. After removing a portion of barrier insulating layer 14 exposed by via 16a, barrier metal layer 18 may be formed on a surface (for example, the entire surface) of second interlayer dielectric layer 16. Barrier metal layer 18 may be uniformly deposited along the internal walls of via 16a and trench 16b. 
Referring to FIG. 1B, copper seed layer 19 may be formed on barrier metal layer 18.
Referring to FIG. 1C, copper layer 20, which may fill via 16a and trench 16b, may be formed on copper seed layer 19, for sample by an electro-chemical plating (ECP).
Referring to FIG. 1D, copper layer 20 may be polished, for example by a CMP process, and insulating layer 16 may thereby be exposed to complete copper metal interconnection 22.
As described above, a multi-metal interconnection may be formed. A barrier insulating layer such as a silicon nitride layer or a silicon carbide may be formed on the formed metal interconnections. The barrier insulating layer may prevent copper ions from diffusing into the interlayer dielectric layer from a copper plating layer formed as the metal interconnection and may also function as an etch stop layer when a damascene pattern for the metal interconnection may be formed. The barrier insulating layer may be non-selectively formed on an entire surface of a substrate after the metal interconnection may be formed.
However, because a device may be highly integrated, a size of a pattern may be significantly reduced. Therefore, the non-selectively formed barrier insulating layer may not sufficiently to prevent diffusion. That is, it may be beneficial for the barrier insulating layer to be uniformly formed, and this may be beneficial for the metal interconnection having a minute pattern. However, uniformity may degrade in the process of forming the barrier insulating layer. In this instance, a diffusion path of copper may be generated. Therefore, reliability of the copper interconnection may be diminished and the performance of a resulting device may degraded.